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Introduction to SONY’s Stacked CMOS Image Sensor Wafer Integration Technology 2020-05-11

Stacked CMOS image sensor technology is considered essential by many vendors today because reductions in packaging size have shortened the trace between ICs and reduced signal latency. Other benefits included low noise, low electrical loss, and excellent electrical characteristics at high frequency. SONY has developed different technologies to meet the needs of the IC market. Today’s ICs must meet requirements such as a high-level of multi-functional hetero-integration, high transmission efficiency, lightweight, thinness, compact size, low-cost, and low power consumption. These requirements are particularly challenging for IC-level packaging technology. 

In the past, SONY built image sensors and logic ICs on separate silicon substrates before using 3D Through Silicon Via (TSV) technology for vertical integrated packaging. This approach avoided the problem of signal interference in conventional CIS whenwhere pixel sensors and logic ICs must be built on the same silicon substrate. The size of the CIS packaging can also be made smaller. In essence, multiple chips are stacked together like a sandwich to form a 3D vertically stacked 3D package where all the chips’ signal and power are interconnected. SONY then improved the stacking method by using Cu-Cu (copper-copper) connections. Direct connections between the copper pads on the surface of the pixel sensor and logic IC are used instead of having to go through the image sensor or a special connection area. Manufacturers can now produce even smaller CMOS image sensors at a fast rate. This new technology supportsed more flexible pin configurations at a higher density and makes scalable stacked CMOS image sensors a possibility.

SONY has made advances to inter-IC connections within the image sensor. When back-list CMOS image sensors (the upper chip) and logic ICs (the lower chip) are stacked together, their signals are linked through Cu connections. This technique represents a significant improvement over TSV stacking technology in terms of design and layout flexibility since space is not taken up by through-silicon vias. 

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